# M.Tech
**VLSI & Embedded System** Lab

Testing & Verification Lab

Design the following combinational logic circuits using Verilog HDL. Verify the functionality using Verilog HDL testbench.

- Basic 2-input logic gates (NOT, AND, OR, NAND, NOR, EX-OR and EXNOR)

- 1-bit Half Adder (using gate level modeling)

- 1-bit Full Adder (using dataflow modeling)

- 8-bit Ripple Carry Adder (using dataflow modeling)

- 2:1 Multiplexer (using gate level/dataflow modeling)

Testing & Verification Lab

Design the following sequential logic circuits using Verilog HDL. Verify the functionality using Verilog HDL testbench. -D Flipflop, T flipflop, JK flipflop (using behavior modeling)-4-bit counter (using dataflow modeling)

Testing & Verification Lab

Design 1-bit Arithmetic Logic Unit using Dataflow/gate level modeling. The following operations should be performed at a time for 1-bit inputs. Verify using Verilog HDL testbench. Use Task in testbench.-NAND, NOR, EX-NOR and 1-bit full adder

Testing & Verification Lab

Design the finite state machines for the following using Verilog HDL. Verify using

Verilog HDL testbench.

- Sequence detector :1011

- Counter (000 to 111)

### Verilog on Xilinx Vivado

## Testing & Verification Lab

Video will get uploaded on 16/05/2021.

Here we learn how to design your digital circuit on verilog and test it with writing testbench. We will check for error at behaviour, synthesis and implementation level.

For lab file and code file mail to 12422rahulkumar@gmail.com

VLSI System Design Lab

Understand the setup and hold concept and find the maximum operating frequency of the 16-bit parallel adder. Design should at least be capable to run at frequency of 250MHz.

VLSI System Design Lab

To implement the filter equation y = W1*X1 + W2*X2 + W3*X3 + W4*X4

Perform the following task and comment about the optimization in terms of power, area, and speed with and without pipeline architecture

### Using Verilog on Xilinx Vivado

## VLSI System Design Lab

Video will get uploaded on 22/05/2021.

while combining millions of MOS transistors onto a single chip it is very necessary to analyze setup, hold, power, speed, area and other parameters.

For lab file and code mail to 12422rahulkumar@gmail.com

Digital VLSI Design Lab

Plot the input and output characteristics of NMOS and PMOS transistor using tsmc model files

Digital VLSI Design Lab

- Implement the CMOS inverter using Ngspice for given 180nm model library.
- Design resistively loads inverter for given Noise margin specifications.
- Design the inverter which satisfies the given noise margin constraints.
- Design the inverter with minimum size transistor and verify your design for 0.18μ technology using a suitable SPICE code.

Digital VLSI Design Lab

Design and simulate the CMOS inverter in Electric and LTspice. Use 180nm technology libraries.

Digital VLSI Design Lab

Design schematic and layout of NAND, NOR, AND, OR, XOR & Half adder and Full adder using basic logic gates, 2x1 MUX using Transmission gate.

Digital VLSI Design Lab

Design schematic and layout of NAND, NOR, AND, OR, XOR & Half adder and Full adder using basic logic gates, 2x1 MUX using Transmission gate.

### Using NGSpice, Electric Binary & LTSpice

## Digital VLSI Design Lab

Video will get uploaded on 22/05/2021.

Design schematic and layout of digital circuits for some unique specifications like noise margin and other.

For lab file and code mail to 12422rahulkumar@gmail.com

Image Gallery

Design the semiconductor resistor and simulate it for its current-voltage characteristics. Extract the resistance and verify it with Ohm’s law. Observe the effect of temperature on drift velocity, electron mobility and resistance value. Comment on effect of doping on resistance with the help of simulation. Nsub= 1e16 cm-3, Nn-well= 1e18 cm-3, Np+ = 1e19 cm-3

Image Gallery

Simulate PN Junction Diode with the specification as mentioned below. Plot its forward and reverse bias characteristics. Extract the key parameters from the characteristics and verify with the theoretical values. Analyze the diode for electric field, electron mobility, drift velocity and electron density. Also plot the Energy Band Diagram.

Given:- Nn-sub= 1e16 cm-3 (uniform), Np-well= 1e19 cm-3 (Gaussian, Y characteristics length 0.25 um)

Image Gallery

Simulate a 180 nm n-channel MOSFET with specifications as shown below. Plot the transfer and output characteristics. Extract the critical parameters viz. threshold voltage, trans-conductance, drain resistance and subthreshold slope. Plot electron density, total current density, electron mobility, Energy Band Diagram and space charges.

Doping Profiles:

Substrate: Uniform; P-Type; 1e16/cm3

Source and Drain: (1) Gaussian; N-Type; 1e18/cm3; Y-Characteristics length= 0.005 um; dimension (0.01 um * 0.2 um) (2) Gaussian; N-Type; 1e20/cm3; Y-Characteristics length= 0.025 um; dimension (0.15um * 0.02 um) (3) Threshold Voltage Doping Implant; Gaussian; P-Type; 1e18 /cm3; Y-Characteristics length= 0.01 um

### Using Visual TCAD Software

## MOS Devices & Technology Lab

Video will get uploaded on 22/05/2021.

Design & Simulate various MOS devices and observe their characteristics.

For lab file and code mail to 12422rahulkumar@gmail.com