M.Tech VLSI & Embedded System Lab
Verilog on Xilinx Vivado
Testing & Verification Lab
Video will get uploaded on 16/05/2021.
Here we learn how to design your digital circuit on verilog and test it with writing testbench. We will check for error at behaviour, synthesis and implementation level.
For lab file and code file mail to 12422rahulkumar@gmail.com
Using Verilog on Xilinx Vivado
VLSI System Design Lab
Video will get uploaded on 22/05/2021.
while combining millions of MOS transistors onto a single chip it is very necessary to analyze setup, hold, power, speed, area and other parameters.
For lab file and code mail to 12422rahulkumar@gmail.com
Using NGSpice, Electric Binary & LTSpice
Digital VLSI Design Lab
Video will get uploaded on 22/05/2021.
Design schematic and layout of digital circuits for some unique specifications like noise margin and other.
For lab file and code mail to 12422rahulkumar@gmail.com
Using Visual TCAD Software
MOS Devices & Technology Lab
Video will get uploaded on 22/05/2021.
Design & Simulate various MOS devices and observe their characteristics.
For lab file and code mail to 12422rahulkumar@gmail.com
