Traffic light controller using Verilog is very simple. You can design it for different designs and algorithms. Given below code is design code for Traffic Light Controller using Finite State Machine(FSM). In this clock and clear are two input signal and RED, GREEN & YELLOW are 2 bit output signal. In output signal, “01” represents Green light, “10” represents Yellow light and “11” represents Red light. On the clear signal, design will enter into default state and start giving output after clear will go low. Please refer video explanation and code for your help.